Baerilog

Baerilog: Verilog Synthesizer

gate-level synthesis of a behavioral Verilog subset, with an interactive netlist viewer

▾Verilog Source Editor ?
· always@(posedge clk or negedge resetn) → dff
· assign with & | ^ ~ ~^ → gates
· assign with + / - → adder/subtractor (fa)
· assign with < > <= >= → comparator (reuses the subtractor's borrow-out)
· always@(*) if/case/casex, ?:, ==, &&/||, reduction ops, {concat} → mux2 chains

1

▾Synthesis Log ?
· parse / elaboration messages

▾Synthesized Gate-level Verilog Netlist (Read-only) ?
· top-level module instantiating primitive cells, followed by the behavioral definition of each cell used

▾Module Hierarchy?
· click an instance to show or hide its signals — showing one hides its children, so you descend a level at a time
· double-click to expand or collapse the branch
· a memory has no waveform row, so it is shown dimmed and does not respond

▾Netlist Viewer ?
· drag to pan, scroll/pinch to zoom, drag nodes to rearrange, double-click an instance block to drill into it — built with React Flow

Loading netlist viewer…

input port

output port

gate (and/or/xor)

inverting gate (nand/nor/xnor/not)

dff

full adder (fa)

mux (ternary/case)

constant

sub-module instance