· the top-level module instantiating primitive cells, followed by the behavioral definition of each cell used
· read-only, and regenerated on every synthesis
· what the synthesis SAID, and what the design costs, is the Synthesis Log card above; the same netlist as a picture is the Netlist Viewer below
▾Module Hierarchy?
· click an instance to show or hide its signals — showing one hides its children, so you descend a level at a time
· double-click to expand or collapse the branch
· a memory has no waveform row, so it is shown dimmed and does not respond
▾Netlist Viewer
?
· drag to pan, scroll or pinch to zoom - the view refits itself on every new graph
· click a wire to name its net above the diagram and light up every segment of it; Escape, or a click on the background, clears that again
· the zoom buttons step in and out about the centre, and fit brings the whole diagram back - zooming out stops there, so the diagram is never lost in empty space
· double-click a sub-module block to drill into its own netlist; the breadcrumb comes back out
· bundle multi-bit logic collapses same-width cell chains into one N-bit box