Baerilog

Baerilog/Verilog Simulator

Write · Simulate · Watch the waveform — all in the browser

▾Verilog Source Editor ?
· Behavioral subset: module/reg/wire, assign, always @(posedge/negedge/*), initial, if/else, #delay, $display, $finish

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▾Testbench Editor ?
· The stimulus and the checks: everything after the `// ======== TESTBENCH ========` line, which is what splits one file across these two cards
· The memory models a design fetches from — a ROM, a RAM, the `system` wrapper that wires them to the DUT — belong here, not in the design
· Run compiles both halves together, so this is the same one file it always was; Save writes it back out with the marker in place

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No testbench section in this file — add a // ======== TESTBENCH ======== line to split it.

▾Simulation Results ?
· $display output and simulator status

Click Run to simulate…

▾Scoreboard?
· Runs a reference model of the AVR subset alongside the design and compares `pc`, `r0`–`r31` and the memories
· the model implements correct AVR semantics, so a mismatch means the RTL and the ISA disagree

No simulation data yet — run a design to compare it against the model.

▾Module Hierarchy?
· click an instance to show or hide its signals — showing one hides its children, so you descend a level at a time
· double-click to expand or collapse the branch
· a memory has no waveform row, so it is shown dimmed and does not respond
· each name carries its declared bit range, e.g. `d[3:0]`

▾Waveform Viewer ?
· click the chart to move the cursor
· drag right to zoom into a range, drag left to zoom out, double-click to zoom in
· wheel sideways — or shift+wheel — to pan; on a touchscreen one finger zooms and two fingers pan
· drag the divider after the names to widen or narrow that column
· hover a value for its radix menu
· the `[:]` button adds each signal's declared bit range to its name
· show or hide a signal row in the Module Hierarchy panel, not here — click one, or drag to paint a run of them
· a gate-level run asks how deep in the hierarchy to record before it runs — a signal below that depth has no row here, and its name is dimmed in the Module Hierarchy panel

No simulation data yet — run a design to see waveforms.

▾Memory Viewer?
· 2D memory arrays (`reg [w:0] name[hi:lo];`) declared in the design
· attach a hex/bin file so `$readmemh`/`$readmemb` can load it

No memories declared in this design.