Baerilog
Simulator
Synthesizer
Compiler
Practice
Baerilog
: Verilog Simulator
Write · Simulate · Watch the waveform — all in the browser
▾
Verilog Source Editor
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· Behavioral subset: module/reg/wire, assign, always @(posedge/negedge/*), initial, if/else, #delay, $display, $finish
Import File
Select from Examples:
1
▶ Run Simulation
Reset
run for
time units
(set by $finish)
▾
Console
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· $display output and simulator status
Click Run to simulate…
▾
Scoreboard
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· Runs a reference model of the AVR subset alongside the design and compares
pc
,
r0
–
r31
and the memories
· the model implements correct AVR semantics, so a mismatch means the RTL and the ISA disagree
Stop Simulation when mismatching model
after:
time unit
Show detail
No simulation data yet — run a design to compare it against the model.
▾
Module Hierarchy
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· click an instance to show or hide its signals — showing one hides its children, so you descend a level at a time
· double-click to expand or collapse the branch
· a memory has no waveform row, so it is shown dimmed and does not respond
▾
Waveform Viewer
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· click the chart to move the cursor
· drag right to zoom into a range, drag left to zoom out, double-click to zoom in
· wheel sideways — or shift+wheel — to pan; on a touchscreen one finger zooms and two fingers pan
· drag the divider after the names to widen or narrow that column
· hover a value for its radix menu
· show or hide a signal row in the
Module Hierarchy
panel, not here — click one, or drag to paint a run of them
Zoom
+
1.0×
−
Reset
◀
▶
Start
End
Apply
No simulation data yet — run a design to see waveforms.
▾
Memory Viewer
?
· 2D memory arrays (
reg [w:0] name[hi:lo];
) declared in the design
· attach a hex/bin file so
$readmemh
/
$readmemb
can load it
(no memories declared)
Attach file(s)…
Hexadecimal
Binary
No memories declared in this design.